library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

Entity FullAdder is port
  	(	in1, in2, Cin : in std_logic;
		Cout, S	: out std_logic	);
End FullAdder;

Architecture Dataflow of FullAdder is

Begin

	Process(in1, in2, Cin)

    		Variable temp : std_logic; 

     	Begin                      --- Esegue addizzione dopo tempo DELTA 
		       temp := in1 XOR in2; 
		       S <= temp XOR Cin; 
		       Cout <= (in1 AND in2) OR (temp AND Cin); 

	End Process; 
			
End Dataflow;