library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

Entity SerialAdder4 is port
	(	go, clk : in std_logic;
		A,B     : in std_logic_vector (3 downto 0);
		SUM     : out std_logic_vector (3 downto 0);
		ready   : out std_logic;

		fAUX1, fAUX2, fAUX3, CLD, CKDaux, OPA, OPB, RSHA: inout	std_logic
		 
	 	);

End SerialAdder4;


Architecture Structural of SerialAdder4 is

-- signal declarations
signal LDA, LDB,  RSHB   : std_logic;
	--signal  fAUX1,fAUX2, fAUX3, CKDaux, CLD : std_logic;

-- Components declarations

  Component UnivReg port
  	(	LD, RSH, dIN : in std_logic;
		Data : in std_logic_vector(3 downto 0);
		Dout	: out std_logic;	
		DataOut : out std_logic_vector(3 downto 0));
  End Component;

  Component FullAdder port
  	(	in1, in2, Cin : in std_logic;
		Cout, S	: out std_logic	);
  End Component;

  Component FF_DPET port
  	(	clk, D, CL: in std_logic;
		Q	: out std_logic	);
  End Component;

  Component MyMSF port
  	(	go, clk 		    : in std_logic;
		LDA, LDB, CLD	    : out std_logic;
		RSHA, RSHB        : inout std_logic;
		ready, CKD	    : out std_logic
	);
  End Component;

-- Component Linking
Begin

	URA:	UnivReg
		port map (LD => LDA , RSH => RSHA, dIN => OPA, Data => A, Dout => OPA);
	URB:	UnivReg
		port map (LD => LDB , RSH => RSHB, dIN => fAUX1, Data => B, Dout => OPB, DataOut => SUM);

	FA1: FullAdder
		port map (in1 => OPA, in2 => OPB, Cin => fAUX3, Cout => fAUX2, S => fAUX1);

	MyFF:FF_DPET		  
		port map (clk => CKDaux, D => fAUX2, CL => CLD, Q => fAUX3);

	TheMSF: MyMSF 
		port map (go => go, clk => clk, LDA => LDA, LDB => LDB, CKD => CKDaux, CLD => CLD, RSHA => RSHA, RSHB => RSHB, ready => ready);

End Structural;